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| 型號(hào)： | XCS10-3VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 47/83頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 100-VQFP |
| 產(chǎn)品變化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 466 |
| RAM 位總計(jì)： | 6272 |
| 輸入/輸出數(shù)： | 77 |
| 門(mén)數(shù)： | 10000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
51
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
Symbol
Description
Device
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Clocks
TCH
Clock High
All devices
3.0
-
4.0
-
ns
TCL
Clock Low
All devices
3.0
-
4.0
-
ns
Propagation Delays - TTL Outputs(1,2)
TOKPOF
Clock (OK) to Pad, fast
All devices
-
3.3
-
4.5
ns
TOKPOS
Clock (OK to Pad, slew-rate limited
All devices
-
6.9
-
7.0
ns
TOPF
Output (O) to Pad, fast
All devices
-
3.6
-
4.8
ns
TOPS
Output (O) to Pad, slew-rate limited
All devices
-
7.2
-
7.3
ns
TTSHZ
3-state to Pad High-Z (slew-rate independent)
All devices
-
3.0
-
3.8
ns
TTSONF
3-state to Pad active and valid, fast
All devices
-
6.0
-
7.3
ns
TTSONS
3-state to Pad active and valid, slew-rate limited
All devices
-
9.6
-
9.8
ns
Setup and Hold Times
TOOK
Output (O) to clock (OK) setup time
All devices
2.5
-
3.8
-
ns
TOKO
Output (O) to clock (OK) hold time
All devices
0.0
-
0.0
-
ns
TECOK
Clock Enable (EC) to clock (OK) setup time
All devices
2.0
-
2.7
-
ns
TOKEC
Clock Enable (EC) to clock (OK) hold time
All devices
0.0
-
0.5
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
11.5
13.5
ns
TRPO
Delay from GSR input to any Pad
XCS05
-
12.0
-
15.0
ns
XCS10
-
12.5
-
15.7
ns
XCS20
-
13.0
-
16.2
ns
XCS30
-
13.5
-
16.9
ns
XCS40
-
14.0
-
17.5
ns
Notes:
1.
Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
2.
Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
3.
Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
4.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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