參數(shù)資料
型號(hào): XCS10-3VQG100C
廠商: Xilinx Inc
文件頁數(shù): 54/83頁
文件大?。?/td> 0K
描述: IC FPGA 5V C-TEMP 100-VQFP
產(chǎn)品變化通告: Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®
LAB/CLB數(shù): 196
邏輯元件/單元數(shù): 466
RAM 位總計(jì): 6272
輸入/輸出數(shù): 77
門數(shù): 10000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
Spartan and Spartan-XL FPGA Families Data Sheet
58
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan-XL Family Output Flip-Flop, Clock-to-Out
Symbol
Description
Device
Speed Grade
Units
-5
-4
Max
Global Clock to Output using OFF
TICKOF
Fast
XCS05XL
4.6
5.2
ns
XCS10XL
4.9
5.5
ns
XCS20XL
5.2
5.8
ns
XCS30XL
5.5
6.2
ns
XCS40XL
5.8
6.5
ns
Slew Rate Adjustment
TSLOW
For Output SLOW option add
All Devices
1.5
1.7
ns
Notes:
1.
Output delays are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load.
3.
OFF = Output Flip Flop
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