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| 型號(hào)： | XCV100E-7PQ240C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 167/233頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 240-PQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 81920 |
| 輸入/輸出數(shù)： | 158 |
| 門(mén)數(shù)： | 128236 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
DS022-2 (v3.0) March 21, 2014
Module 2 of 4
Production Product Specification
33
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. SelectI/O devices support both classes for
the SSTL2 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.
CTT — Center Tap Terminated
The Center Tap Terminated, or CTT standard is a 3.3V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
AGP-2X — Advanced Graphics Port
The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
LVDS — Low Voltage Differential Signal
LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350mV. The use
of a reference voltage (VREF) or a board termination voltage
(VTT) is not required. LVDS requires the use of two pins per
input or output. LVDS requires external resistor termination.
BLVDS — Bus LVDS
This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termi-
nation is different than the one for standard LVDS.
LVPECL — Low Voltage Positive Emitter Coupled
Logic
LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
The use of a reference voltage (VREF) or a board termina-
tion voltage (VTT) is not required. The LVPECL standard
requires external resistor termination.
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O fea-
tures. Most of these symbols represent variations of the five
generic SelectI/O symbols.
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUF
Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in Figure 37. The extension
to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.
The following list details the variations of the IBUF symbol:
IBUF
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI66_3
IBUF_GTL
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
IBUF_AGP
IBUF_LVCMOS18
IBUF_LVDS
IBUF_LVPECL
When the IBUF symbol supports an I/O standard that
requires a VREF, the IBUF automatically configures as a dif-
ferential amplifier input buffer. The VREF voltage must be
supplied on the VREF pins. In the case of LVDS, LVPECL,
and BLVDS, VREF is not required.
Figure 37: Input Buffer (IBUF) Symbols
O
I
IBUF
x133_01_111699
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| XCV100E-7PQ240I | 功能描述:IC FPGA 1.8V I-TEMP 240-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV100E-8BG240C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-8BG240I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-8BG352C | 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV100E-8BG352I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
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