參數(shù)資料
型號(hào): XCV100E-7PQ240C
廠商: Xilinx Inc
文件頁(yè)數(shù): 183/233頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 240-PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Virtex®-E
LAB/CLB數(shù): 600
邏輯元件/單元數(shù): 2700
RAM 位總計(jì): 81920
輸入/輸出數(shù): 158
門數(shù): 128236
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 240-BFQFP
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
DS022-2 (v3.0) March 21, 2014
Module 2 of 4
Production Product Specification
47
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Termination Resistor Packs
Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at http://www.bourns.com
.
LVDS Design Guide
The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
Creating LVDS Global Clock Input Buffers
Global clock input buffers can be combined with adjacent
IOBs to form LVDS clock input buffers. P-side is the GCLK-
PAD location; N-side is the adjacent IO_LVDS_DLL site.
HDL Instantiation
Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
VHDL Instantiation
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
Location constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
NET clk_external LOC = GCLKPAD3;
GCLKPAD3 can also be replaced with the package pin
name such as D17 for the BG432 package.
Table 40: Bourns LVDS/LVPECL Resistor Packs
Part Number
I/O Standard
Term.
for:
Pairs/
Pack
Pins
CAT16
LV2F6
LVDS
Driver
2
8
CAT16
LV4F12
LVDS
Driver
4
16
CAT16
PC2F6
LVPECL
Driver
2
8
CAT16
PC4F12
LVPECL
Driver
4
16
CAT16
PT2F2
LVDS/LVPECL
Receiver
2
8
CAT16
PT4F4
LVDS/LVPECL
Receiver
4
16
Figure 58: LVDS elements
O
I
IBUF_LVDS
O
I
OBUF_LVDS
IOBUF_LVDS
O
T
I
OBUFT_LVDS
O
I
IBUFG_LVDS
IO
T
I
x133_22_122299
Table 41: Global Clock Input Buffer Pair Locations
Pkg
GCLK 3
GCLK 2
GCLK 1
GCLK 0
PN
P
N
P
N
P
N
CS144
A6
C6
A7
B7
M7
M6
K7
N8
PQ240
P213
P215
P210 P209
P89
P87
P92
P93
HQ240
P213
P215
P210 P209
P89
P87
P92
P93
BG352
D14
A15
B14
A13
AF14
AD14
AE13
AC13
BG432
D17
C17
A16
B16
AK16
AL17
AL16
AH15
BG560
A17
C18
D17
E17
AJ17
AM18
AL17
AM17
FG256
B8
A7
C9
A8
R8
T8
N8
N9
FG456
C11
B11
A11
D11
Yll
AA11
W12
U12
FG676
E13
B13
C13
F14
AB13
AF13
AA14
AC14
FG680
A20
C22
D21
A19
AU22
AT22
AW19
AT21
FG860
C22
A22
B22
D22
AY22
AW21
BA22
AW20
FG900
C15
A15
E15
E16
AK16
AH16
AJ16
AF16
FG1156
E17
C17
D17
J18
Al19
AL17
AH18
AM18
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XCV100E-7PQ240I 功能描述:IC FPGA 1.8V I-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV100E-8BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
XCV100E-8BG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays
XCV100E-8BG352C 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV100E-8BG352I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays