參數(shù)資料
型號(hào)： XCV200E-7CS144C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 184/233頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 1.8V C-TEMP 144-CSBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 198
系列： Virtex®-E
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 114688
輸入/輸出數(shù)： 94
門(mén)數(shù)： 306393
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-LCSBGA（12x12）
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
48
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Optional N-side
Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.
VHDL Instantiation
gclk0_p : IBUFG_LVDS port map
(I=>clk_p_external, O=>clk_internal);
gclk0_n : IBUFG_LVDS port map
(I=>clk_n_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_p_external),
.O(clk_internal));
IBUFG_LVDS gclk0_n (.I(clk_n_external),
.O(clk_internal));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
NET clk_p_external LOC = GCLKPAD3;
NET clk_n_external LOC = C17;
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
VHDL Instantiation
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
Verilog Instantiation
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the .ucf or .ncf file.
NET data<0> LOC = D28; # IO_L0P
Optional N-side
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
VHDL Instantiation
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
Verilog Instantiation
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
IBUF_LVDS data0_n (.I(data_n[0]), .O());
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Adding an Input Register
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthesis
macro libraries available to explicitly create these structures.
The input library macros are listed in Table 42. The I and IB
inputs to the macros are the external net connections.
相關(guān)PDF資料
PDF描述
XCV200E-6CS144I IC FPGA 1.8V I-TEMP 144-CSBGA
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4-745130-4 SHLDING FERRULE,PLTD,BULK PKG
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV200E-7CS144I 功能描述:IC FPGA 1.8V I-TEMP 144-CSBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV200E-7FG240C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays
XCV200E-7FG240I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays
XCV200E-7FG256C 功能描述:IC FPGA 1.8V C-TEMP 256-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV200E-7FG256I 功能描述:IC FPGA 1.8V I-TEMP 256-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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