參數(shù)資料
型號: XE3005I033TRLF
廠商: Semtech
文件頁數(shù): 3/37頁
文件大小: 0K
描述: IC CODEC LOW PWR 16BIT 20-TSSOP
標(biāo)準(zhǔn)包裝: 1
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 16 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 78 / 78
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 78 / 78
電壓 - 電源,模擬: 1.8 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.8 V ~ 3.6 V
工作溫度: -20°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: XE3005I033DKR
Semtech 2005
www.semtech.com
11
XE3005/XE3006
The above illustration is valid for either the SMAD output as a result of AIN/SDO or for the SMDA output as a
function of AOUT/SDI.
2.1.10 Start-up and Initialization
The CODEC generates its own power on reset signal after a power supply is connected to the VDD pin. The reset signal
is made available for the user at the pin NRESET. The rising edge of the NRESET indicates that the startup sequence of
the CODEC has finished. In most applications the NRESET pin can be left open.
The NRESET signal generated by the CODEC is used to initialize the various blocks in the device and guarantees a
correct start-up of the circuit. The start-up sequence that is automatically carried out upon power-up of the device is listed
below and illustrated in Figure 10.
1.
NRESET is low (0V) when the device is not powered and remains low for a short time when VDD (upper curve in
Figure 10) is applied. The low state sustains while VDD, VREG16, VREF are stabilizing.
2.
As soon as the MCLK signal is present, a counter is activated that counts 2
21 periods of the MCLK. After this
moment the NRESET is in the high state (VDD).
VREG16 = 1.6V
VREF = 1.2V
VDD = 1.8..3.3V
977 ms (MCLK=2.048KHz)
main reset
NRESET
time
MCLK
. . .
Figure 11: Startup sequence and NRESET signal after power-on.
The user can use the NRESET pin in 3 different ways and combinations:
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