![](http://datasheet.mmic.net.cn/Semtech/XE3005I064TRLF_datasheet_107232/XE3005I064TRLF_16.png)
Semtech 2005
www.semtech.com
16
XE3005/XE3006
-
Disable time (t disable) between the last rising edge of SCK and the rising edge of SS.
-
SCK frequency (FSCK)
Delay
Min
Max
Unit
Comments
t recover
125
-
ns
t disable
2 x Tmaster
-
ns
Tmaster = clock period of the master clock MCLK
F SCK
0.5 x Fmaster
Hz
Fmaster = frequency of the master clock MCLK
3.3.2
SPI Interface Modes
There are two SPI modes: read and write.
3.3.2.1
Read Mode
Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line. The
content of the addressed register, one byte, is dumped on the MISO line during the transmission of the second byte on
the MOSI. The formats of one byte are the following:
bit
7
6
5
4
3
2
1
0
mosi
1
0
msb
A (4:0)
lsb
bit
7
6
5
4
3
2
1
0
miso
msb
D(7:0)
lsb
ss
sck
mosi
miso
request (read <address A(4:0)>)
read data D(7:0) of address A(4:0)
msb
lsb
A1
0
1
A4
A2
A0
A3
1
0
Figure 17: SPI signal timing in read mode
3.3.2.2
Write Mode
Write communication always takes place in pairs of bytes. The format of the 2 bytes is:
Bit
7
6
5
4
3
2
1
0
mosi
1
0
msb
A(4:0)
lsb
Bit
7
6
5
4
3
2
1
0
mosi
msb
D(7:0)
lsb