參數(shù)資料
型號： XE3005I033TRLF
廠商： Semtech
文件頁數(shù)： 7/37頁
文件大小： 0K
描述： IC CODEC LOW PWR 16BIT 20-TSSOP
標(biāo)準(zhǔn)包裝： 1
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 16 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 78 / 78
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 78 / 78
電壓 - 電源，模擬： 1.8 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.8 V ~ 3.6 V
工作溫度： -20°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
其它名稱： XE3005I033DKR
Semtech 2005
www.semtech.com
15
XE3005/XE3006
Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without
reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely omitted and
the 3 SPI pins can be fixed to ‘0’ or ‘1’.
2.
Programming through SPI interface after power-up
Once the device has been powered up, the configuration registers can be modified at all times (also when the device is
active) through the SPI interface.
The following section describes the SPI protocol which is required to change the control registers from their default
values.
3.3
SERIAL PERIPHERAL INTERFACE - SPI
The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as a
microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the
communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a master (e.g.
DSP).
Four lines are used to transmit data between the slave and master:
-
MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK).
-
MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK).
-
SCK (Serial Clock) synchronizes the data bits of MOSI and MISO.
-
SS (Slave Select) Slave devices are selected by activating SS.
3.3.1
Protocol
During SPI communication, data is simultaneously transmitted and received.
0
1
15
SS
SCK
MOSI
MISO
15
0
14
1
tdisable
1/Fsck
trecovery
…
Figure 16: SPI signal timing
The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of SCK.
The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising edge of SCK.
Transmission in either direction is by 2 bytes with MSB first.
The SS pin should be kept low during the whole transfer of data.
There are three timing constraints:
-
Recovery time (t recovery) between the falling edge of SS and the falling edge of SCK.
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