參數(shù)資料
型號(hào)： XE8000EV121
廠商： Semtech
文件頁(yè)數(shù)： 6/53頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR SX8723/24
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，傳感器至模數(shù)轉(zhuǎn)換器接口，可編程
嵌入式： 否
已用 IC / 零件： SX8723，SX8724，SX8725
主要屬性： 用于橋型傳感器的信號(hào)調(diào)節(jié)
次要屬性： GUI，最多 16 位，1/12 ~ 1000 可編程增益，I2C 接口
已供物品： 板，CD
產(chǎn)品目錄頁(yè)面： 585 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： SX8725E083DKR-ND - IC DAS PRESSURE/TEMP SENS 12MLPD
SX8724E082DKR-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ
SX8725E083CT-ND - IC DAS PRESSURE/TEMP SENS 12MLPD
SX8724E082CT-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ
SX8725E083TR-ND - IC DAS PRESSURE/TEMP SENS 12MLPD
SX8724E082TR-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ
ADVANCED COMMUNICATIONS & SENSING
V1.23 2009 Semtech Corp.
www.semtech.com
14
SX8724
ZoomingADC for Pressure and Temperature Sensing
2-WIRE
The 2-WIRE interface gives access to the chip registers. It complies with the 2-WIRE protocol specifications,
restricted to the slave side of the communication.
General features:
Slave only operation
Fast mode operation (up to 400 kHz)
Combined read and write mode support
General call reset support
7-bit device address customization
Stretch 2-WIRE clock SCL only before sending ACK/NACK
The interface handles 2-WIRE communication at the transaction level: the processor is only aware of read and
writes transactions. A read transaction is an external request to get the content of system memory location and
a write transaction is an external request to write the content of a system memory location.
2-WIRE Communication Format
Figure 5 - Timing Diagram for Reading from SX8724
Figure 6 - Timing Diagram for Writing to the SX8724
Figure 7 - Timing Diagram for Reading an ADC Sample from SX8724
2-WIRE Address
The default 2-WIRE slave address is 1001000 in binary.
This is the standard part 2-WIRE slave address. Other addresses between 1001001 and 1001111 are available
by special request.
Start
Slave Address
ACK
W
Memory Address
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Start
Slave Address
ACK
W
Memory Address
ACK
Start
Slave Address
ACK
W
Data
ACK Stop
Master
SX8724
Master
SX8724
Master
SX8724
1
9
1
9
1
9
1
9
1
0
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
SDA
SCL
Start
Slave Address
ACK
W
RegACOutMsb
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Ready
1
0
1
Start
Slave Address
ACK
W
RegACOutLsb
ACK
Start
Slave Address
ACK
R
Data
NACK Stop
Master
SX8724
1
0
1
0
1
9
1
9
1
9
1
9
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
SDA
SCL
Ready
1
0
...
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