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| 型號(hào)： | XIO2200AGGW |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 136/202頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產(chǎn)品培訓(xùn)模塊： | PCI Express Basics |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 應(yīng)用： | PCI Express 至 PCI 轉(zhuǎn)換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁(yè)面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19617 |
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Feature/Protocol Descriptions
26
March 5 2007 June 2011
SCPS154C
3.4.3 PCI Express Extended VC With VC Arbitration
When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted
access to the upstream PCI Express link. These three arbitration modes include strict priority, hardware-fixed
round-robin, and 32-phase WRR. The default mode is strict priority. For all three arbitration modes, if the
second VC is disabled, then VC0 is always granted.
To map upstream transactions to the extended VC, the following registers must be programmed:
1. Bit 0 (ISOC_ENABLE) is asserted in the upstream isochrony control register at device control memory
window register offset 04h (see Section 6.4).
2. At least one PCI isochronous window register set must be programmed. Please see Section 3.4.2 for a
description on how to program this advanced feature.
3. The traffic class ID selected for the PCI isochronous window(s) must be assigned to the extended VC.
This is accomplished by asserting the corresponding bit in the TC_VC_MAP field in the VC resource
control register (VC1) at PCI Express extended register offset 170h (see Section 5.25).
4. The extended VC must be enabled. This is accomplished by asserting bit 31 (VC_EN) and programming
bits 26:24 (VC_ID) in the VC resource control register (VC1) at PCI Express extended register offset 170h.
3.4.3.1
Strict Priority Arbitration Mode
Strict priority arbitration always grants VC1 traffic over VC0 traffic. If the traffic on VC1 uses 100% of the
upstream link bandwidth, then VC0 traffic is blocked. This mode is enabled when bit 25
(STRICT_PRIORITY_EN) in the general control register at offset D4h equals 1b (see Section 4.65).
For applications that require QoS or isochronous operation, this arbitration mode is recommended. In this
mode, all traffic on VC1 is assured access to the upstream link and VC0 traffic is best effort with a lower priority.
3.4.3.2
Hardware-Fixed, Round-Robin Arbitration
Hardware-fixed, round-robin arbitration alternates between VC0 and the second VC. Over an extended period
of time, if both VCs are heavily loaded with equal data payloads, then each VC is granted approximately 50%
of the upstream link bandwidth. The PCI configuration registers described in Table 38 configure the
hardware-fixed, round-robin arbitration mode.
Table 38. Hardware-Fixed, Round-Robin Arbiter Registers
PCI OFFSET
REGISTER NAME
DESCRIPTION
Classic PCI configuration
register D4h
General control
(see Section 4.65)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Classic PCI configuration
register 15Ch
Port VC control
(see Section 5.19)
Bits 3:1 (VC_ARB_SELECT) equal to 000b enable hardware-fixed, round-robin
arbitration mode.
3.4.3.3
32-Phase, WRR Arbitration Mode
When the second upstream VC is enabled, the VC arbiter selects the next PCI Express upstream link
transaction based on entries within a VC arbitration table. There are actually two VC arbitration tables within
the bridge. The first table is accessed through the extended PCI Express configuration register space using
configuration read/write transactions. The second table is internal and is used by the VC arbiter to make
selection decisions. A configuration register load function exists to transfer the contents of the configuration
register table to the internal table.
The VC arbitration table uses a 4-bit field to identify the VC that is selected during each arbiter cycle. Bits 2:0
of this 4-bit field are loaded with the VC_ID assigned to each VC. For the arbiter to recognize a VC request,
the software must allocate only 1 phase to the same VC_ID.
The PCI configuration registers described in Table 39 configure the 32-phase, WRR arbitration mode.
Not Recommended for New Designs
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| XIO2200ZGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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