參數(shù)資料
型號(hào): XPC7455RX600NC
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 4/12頁
文件大?。?/td> 336K
代理商: XPC7455RX600NC
4
MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
General Parameters
Table 8 provides the clock AC timing specifications for the MPC7455 part numbers described herein.
Table 12 provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7455 part numbers
described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
600 MHz
733 MHz
800 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
f
core
500
600
500
733
500
800
MHz
1
VCO frequency
f
VCO
1000
1200
1000
1466
1000
1600
MHz
1
Notes
:
1.
Caution
: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies (see Table 4 in the
MPC7455 RISC Microprocessor Hardware Specifications
). Refer to the
PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4] settings.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades
Unit
Notes
L2CR[12] = 0 and L3CR[12] = 0
8
L2CR[12] = 1 and L3CR[12] = 1
8
Min
Max
Min
Max
L3_CLK rise and
fall time
t
L3CR
,
t
L3CF
1.0
1.0
ns
1
Setup times:
Data and parity
t
L3DVEH
,
t
L3DVEL
–0.1
–0.1
ns
2, 3, 4
Input hold times:
Data and parity
t
L3DXEH
,
t
L3DXEL
t
L3_ECHO_CLK
/4
+ 0.6
t
L3_ECHO_CLK
/4
+0.6
ns
2, 4
Valid times:
Data and parity
t
L3CHDV
,
t
L3CLDV
(– t
L3_CLK
/4)
+ 0.4
(– t
L3_CLK
/4)
+ 0.8
ns
5, 6, 7
Valid times:
All other outputs
t
L3CHOV
t
L3_CLK
/4 + 1.0
t
L3_CLK
/4 + 1.2
ns
5, 7
Output hold times:
Data and parity
t
L3CHDX
,
t
L3CLDX,
t
L3_CLK
/4 – 0.4
t
L3_CLK
/4 – 0.2
ns
5, 6, 7
Output hold times:
All other outputs
t
L3CHOX
t
L3_CLK
/4 – 0.5
t
L3_CLK
/4 – 0.3
ns
5, 7
L3_CLK to high
impedance:
Data and parity
t
L3CLDZ
t
L3_CLK
/2
t
L3_CLK
/2
ns
F
Freescale Semiconductor, Inc.
n
.
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