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參數(shù)資料
| 型號： | XPC7455RX600NC |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 336K |
| 代理商： | XPC7455RX600NC |
6
MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
General Parameters
Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455
part numbers described herein.
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades
Unit
Notes
L2CR[12]=0 and L3CR[12]=0
6
L2CR[12]=1 and L3CR[12]=1
6
Min
Max
Min
Max
L3_CLK rise and fall
time
t
L3CR
,
t
L3CF
—
1.0
—
1.0
ns
1, 5
Setup times:
Data and parity
t
L3DVEH
1.5
—
1.5
—
ns
2, 5
Input hold times:
Data and parity
t
L3DXEH
—
0.5
—
0.5
ns
2, 5
Valid times:
Data and parity
t
L3CHDV
—
t
L3_CLK
/4 + 1.0
—
t
L3_CLK
/4 + 1.2
ns
3, 4, 5
Valid times:
All other outputs
t
L3CHOV
—
t
L3_CLK
/4 + 1.0
—
t
L3_CLK
/4 + 1.2
ns
4
Output hold times:
Data and parity
t
L3CHDX
t
L3_CLK
/4 – 0.4
—
t
L3_CLK
/4 – 0.2
—
ns
3, 4, 5
Output hold times:
All other outputs
t
L3CHOX
t
L3_CLK
/4 – 0.4
—
t
L3_CLK
/4 – 0.2
—
ns
4, 5
L3_CLK to high
impedance:
Data and parity
t
L3CHDZ
—
2.0
—
2.0
ns
5
L3_CLK to high
impedance:
All other outputs
t
L3CHOZ
—
2.0
—
2.0
ns
5
Notes
:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
DD
.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
edge of the input L3_ECHO_CLK
n
(see
Figure 10 in the
MPC7455 RISC Microprocessor Hardware Specifications
).
Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLK
n
to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-
load (see Figure 10 in the
MPC7455 RISC Microprocessor Hardware Specifications
).
4. t
L3_CLK
/4 is one-fourth the period of L3_CLK
n
. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
5. Timing behavior and characterization are currently being evaluated.
6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or
both cleared; other configurations will increase t
L3CSKW1
and t
L3CSKW2
, which may cause unreliable L3 operation.
F
Freescale Semiconductor, Inc.
n
.
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