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參數(shù)資料
| 型號： | XPC7455RX600NC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 336K |
| 代理商： | XPC7455RX600NC |
MOTOROLA
MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
7
General Parameters
1.9.1 PLL Configuration
The MPC7455 PLL is configured by the PLL_CFG[0:4] signals; note that PLL_CFG[4] was formerly called
PLL_EXT in earlier documentation. For a given SYSCLK (bus) frequency, the PLL configuration signals
set the internal CPU and VCO frequency of operation. PLL_CFG[4] will normally be pulled low but can be
asserted for extended modes of operation. The PLL configuration for the MPC7455 is shown in Table 17
for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK
frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz column in Table 8.
Note that the settings for Rev. C devices are different than those for subsequent devices.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 800-MHz Parts
PLL_CFG
[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83 MHz
Bus
100 MHz
Bus
133 MHz
00000
0.5x
2x
01000
2x
2x
01100
2.5x
2x
10000
3x
2x
11100
3.5x
2x
10100
4x
2x
533
(1066)
01110
4.5x
2x
600
(1200)
10110
5x
2x
500
(1000)
667
(1333)
10010
5.5x
2x
550
(1100)
733
(1466)
11010
6x
2x
600
(1200)
800
(1600)
01010
6.5x
2x
540
(1080)
650
(1300)
00100
7x
2x
525
(1050)
580
(1160)
700
(1400)
00010
7.5x
2x
500
(1000)
563
(1125)
623
(1245)
750
(1500)
11000
8x
2x
533
(1066)
600
(1200)
664
(1328)
800
(1600)
01111
9x
2x
600
(1200)
675
(1350)
747
(1494)
F
Freescale Semiconductor, Inc.
n
.
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