參數(shù)資料
型號： XPC850DECZT66BU
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 5/76頁
文件大小： 825K
代理商： XPC850DECZT66BU
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
5
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example,
transmission after the current frame is finished or immediately if no frame is
being sent and
CLOSE
RXBD
closes the receive buffer descriptor)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight
for the four USB endpoints
— Three parallel I/O registers with open-drain capability
Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC
(all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
GRACEFUL
STOP
TRANSMIT
stops
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參數(shù)描述
XPC850DECZT80B 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Communications Controller Hardware Specifications
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