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參數(shù)資料
| 型號(hào)： | XQR4013XL-3CB228M |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 201K |
| 代理商： | XQR4013XL-3CB228M |
QPRO XQR4000XL Radiation Hardened FPGAs
DS071 (v1.1) June 25, 2000
Product Specification
This Material Copyrighted by Its Respective Manufacturer
1-800-255-7778XQR4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out
(1,2,3)
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
Symbol
Description
Device
-3
Units
Min
Max
T
ICKOF
Global low skew clock to output using OFF
(4)
XQR4013XL
1.5
8.6
ns
XQR4036XL
2.0
9.8
ns
XQR4062XL
2.3
11.3
ns
T
SLOW
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible
column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as
determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case
pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations.
3.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load.
4.
OFF = Output Flip-Flop
For output SLOW option add
All Devices
3.0
3.0
ns
Symbol
Description
Device
-3
Units
Min
Max
T
ICKEOF
Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6.
XQR4013XL
1.3
7.4
ns
XQR4036XL
1.2
8.1
ns
XQR4062XL
1.2
9.9
ns
Notes:
1.
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as
determined by the static timing analyzer (TRCE) can be added to the AC parameter T
OKPOF
and used as a worst-case
pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load.
2.
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