R
XQR4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values are
expressed in nanoseconds unless otherwise noted.
Symbol
Description
-3
Units
Min
Max
Clocks
T
CH
T
CL
Clock High
3.0
-
ns
Clock Low
3.0
-
ns
Propagation Delays
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OFPF
T
OKFPF
Setup and Hold Times
Clock (OK) to pad
-
5.0
ns
Output (O) to pad
-
4.1
ns
High-Z to pad High-Z (slew-rate independent)
-
4.4
ns
High-Z to pad active and valid
-
4.1
ns
Output (O) to pad via fast output MUX
-
5.5
ns
Select (OK) to pad via fast MUX
-
5.1
ns
T
OOK
T
OKO
T
ECOK
T
OKEC
Global Set/Reset
Output (O) to clock (OK) setup time
0.5
-
ns
Output (O) to clock (OK) hold time
0
-
ns
Clock Enable (EC) to clock (OK) setup time
0
-
ns
Clock Enable (EC) to clock (OK) hold time
0.3
-
ns
T
MRW
T
RPO
Minimum GSR pulse width
Delay from GSR input to any pad
(2)
19.8
-
ns
XQR4013XL
-
20.5
ns
XQR4036XL
-
27.1
ns
XQR4062XL
-
33.7
ns
Slew Rate Adjustment
T
SLOW
Notes:
1.
Output timing is measured at ~50% V
CC
threshold, with 50 pF external capacitive loads.
2.
Indicates Minimum Amount of Time to Assure Valid Data.
For output SLOW option add
-
3.0
ns
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