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參數(shù)資料
| 型號： | XR16C2850CP40 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 25/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850CP40 |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
25
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be
used for automatic hardware flow control by enabled
by EFR bit-6. If the modem interface is not used, this
output may be used as a general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2850.
But it is available for use during Internal Loopback
Mode. In the Loopback Mode, this bit is used to write
the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, in-
terrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
Logic 0 = INT (A-B) outputs disabled (three state
mode) and OP2# output set to a logic 1 (default).
Logic 1 = INT (A-B) outputs enabled (active mode)
and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loop-
back section and Figure 13.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550
compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode,
any RX character received will resume transmit
operation. The RX character will be loaded into the
RX FIFO , unless the RX character is an Xon or
Xoff character and the 2850 is programmed to use
the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. The TX/RX output/input are routed
to the infrared encoder/decoder. The data input and
output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX
output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
4.8
L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
This register provides the status of data transfers be-
tween the UART and the host. If IER bit-2 is set to a
logic 1, an LSR interrupt will be generated immediate-
ly when any character in the RX FIFO has an error
(parity, framing, overrun, break).
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or
FIFO (default).
Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condi-
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error. If IER bit-
2 is set, an interrupt will be generated immediately.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR
does not have correct parity information and is sus-
pect. This error is associated with the character
available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX
was a logic 0 for at least one character frame time).
In the FIFO mode, only one break character is
loaded into the FIFO. The break indication remains
until the RX input returns to the idle condition,
“mark” or logic 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2850IJ44 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IM48 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IP40 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850CJ | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850CM | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IJ | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| XR16C2850IJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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