參數(shù)資料
型號： XR16C2850CP40
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 43/43頁
文件大?。?/td> 611K
代理商： XR16C2850CP40
XR16C2850
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
á
II
T
ABLE
8: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1................................................ 19
4.0 INTERNAL Register descriptions ........................................................................................ 20
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
- O
NLY
........................................................................... 20
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-O
NLY
......................................................................... 20
4.3 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
........................................................................... 20
4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 20
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 20
4.4 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 21
4.4.1 Interrupt Generation: ................................................................................................................................ 21
4.4.2 Interrupt Clearing:..................................................................................................................................... 22
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................... 22
4.5 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 22
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
.................................................................................................... 23
4.6 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................. 24
4.7 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
........ 24
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................................................................ 24
4.8 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
..................................................................................... 25
4.9 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................... 26
4.10 S
CRATCH
P
AD
R
EGISTER
(SPR) - R
EAD
/W
RITE
............................................................................... 26
4.11 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR) ................................................................................. 27
T
ABLE
12: S
CRATCHPAD
S
WAP
S
ELECTION
............................................................................................................................................ 27
T
ABLE
13: A
UTO
RTS H
YSTERESIS
....................................................................................................................................................... 27
4.12 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
................................................................................... 27
4.13 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
............................................... 27
4.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
.................................................................. 27
4.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 27
4.16 T
RIGGER
L
EVEL
/ FIFO D
ATA
C
OUNT
R
EGISTER
(TRG) - W
RITE
-O
NLY
............................................. 27
4.17 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
............................................................................ 27
4.18 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/W
RITE
.................................................................... 28
T
ABLE
14: T
RIGGER
T
ABLE
S
ELECT
....................................................................................................................................................... 28
4.19 E
NHANCED
F
EATURE
R
EGISTER
(EFR) ............................................................................................ 28
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 29
4.20 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 30
T
ABLE
16: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 30
ABSOLUTE MAXIMUM RATINGS...................................................................................31
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)31
ELECTRICAL CHARACTERISTICS................................................................................31
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................31
AC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................32
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
3.3
OR
5.0V ±10% .............32
F
IGURE
14. C
LOCK
T
IMING
.................................................................................................................................................................... 33
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A & B......................................................................................................... 33
F
IGURE
16. D
ATA
B
US
R
EAD
T
IMING
..................................................................................................................................................... 34
F
IGURE
17. D
ATA
B
US
W
RITE
T
IMING
.................................................................................................................................................... 34
F
IGURE
18. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B................................................................. 35
F
IGURE
19. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B............................................................... 35
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A & B ............................................... 36
F
IGURE
21. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A & B................................................ 36
F
IGURE
22. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B................................... 37
F
IGURE
23. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B.................................... 37
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................38
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................39
PACKAGE DIMENSIONS (40 PIN PDIP).........................................................................40
R
EVISION
H
ISTORY
....................................................................................................................................41
TABLE OF CONTENTS ................................................................................................................................. I
相關(guān)PDF資料
PDF描述
XR16C2850IJ44 3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850IM48 3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850IP40 3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850CJ DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850CM DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16C2850IJ 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:
XR16C2850IJ44 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850IJ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2850IJTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2850IM 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
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