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參數(shù)資料
| 型號： | XR16C2850CP40 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 3/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850CP40 |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
3
PIN DESCRIPTIONS
N
AME
40-PDIP
P
IN
#
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
26
27
28
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
21
24
19
I
Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines A2:A0. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
IOR# must never be active together with IOW#.
IOW#
18
20
15
I
Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines. IOW# must never be
active together with IOR#.
CSA#
CSB#
14
15
16
17
10
11
I
UART channel select (active low) to enable UART chan-
nel A or B in the device for data bus operation.
INTA
INTB
30
29
33
32
30
29
O
UART channel A or B Interrupt output. The output state is
defined by the user through the software setting of
MCR[3]. INTA or INTB is set to the active mode and
OP2A# or OP2B# output to a logic 0 when MCR[3] is set
to a logic 1. INTA or INTB is set to the three state mode
and OP2A# or OP2B# to a logic 1 when MCR[3] is set to
a logic 0 (default). See MCR[3].
TXRDYA#
TXRDYB#
-
-
1
12
43
6
O
UART channel A or B Transmitter Ready (active low).
The output provides the TX FIFO/THR status for transmit
channel A or B. See Table 2 on page 8. If it is not used,
leave it unconnected.
RXRDYA#
RXRDYB#
-
-
34
23
31
18
O
UART channel A or B Receiver Ready (active low). This
output provides the RX FIFO/RHR status for receive
channel A or B. See Table 2 on page 8. If it is not used,
leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
11
12
13
14
7
8
O
UART channel A or B Transmit Data or infrared encoder
data. Standard transmit and receive interface is enabled
when MCR[6] = 0. In this mode, the TX signal will be a
logic 1 during reset or idle (no data). Infrared IrDA trans-
mit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If it is not
used, leave it unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2850IJ44 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IM48 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IP40 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850CJ | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850CM | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IJ | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| XR16C2850IJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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