參數(shù)資料
型號： XR16C2850IM48
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù)： 42/43頁
文件大?。?/td> 611K
代理商： XR16C2850IM48
á
XR16C2850
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
.............................................................................................................................................1
F
EATURES
..................................................................................................................................................1
F
IGURE
1. XR16C2850 B
LOCK
D
IAGRAM
................................................................................................................................................ 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
............................................................................................................................................................. 2
ORDERING
INFORMATION
.............................................................................................................................2
PIN DESCRIPTIONS..........................................................................................................3
DATA BUS INTERFACE...........................................................................................................................3
MODEM OR SERIAL I/O INTERFACE.....................................................................................................3
ANCILLARY SIGNALS..............................................................................................................................4
1.0 Product DESCRIPTION ........................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................... 7
2.1 CPU I
NTERFACE
................................................................................................................................. 7
F
IGURE
3. XR16C2850 D
ATA
B
US
I
NTERCONNECTIONS
......................................................................................................................... 7
2.2 D
EVICE
R
ESET
.................................................................................................................................... 7
2.3 D
EVICE
I
DENTIFICATION
AND
R
EVISION
................................................................................................ 7
2.4 C
HANNEL
A
AND
B S
ELECTION
............................................................................................................ 7
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
....................................................................................................................................................... 7
2.5 C
HANNEL
A
AND
B I
NTERNAL
R
EGISTERS
............................................................................................ 8
2.6 DMA M
ODE
........................................................................................................................................ 8
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
.................................................................................................... 8
2.7 INTA
AND
INTB O
UPUTS
.................................................................................................................... 8
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
................................................................................................................ 8
2.8 C
RYSTAL
O
SCILLATOR
OR
E
XT
. C
LOCK
I
NPUT
...................................................................................... 9
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
....................................................................................................................... 9
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
........................................................................................................................................ 9
2.9 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
........................................................................................... 9
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
................................................................................................... 9
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
............................................................................................................................ 10
T
ABLE
5: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
.............................................................................. 10
2.10 T
RANSMITTER
................................................................................................................................. 11
2.10.1 Transmit Holding Register (THR) - Write Only....................................................................................... 11
2.10.2 Transmitter Operation in non-FIFO Mode.............................................................................................. 11
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
...................................................................................................................... 11
2.10.3 Transmitter Operation in FIFO Mode ..................................................................................................... 11
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
............................................................................................. 11
2.11 R
ECEIVER
....................................................................................................................................... 12
2.11.1 Receive Holding Register (RHR) - Read-Only....................................................................................... 12
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
........................................................................................................................... 12
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
............................................................................... 13
2.12 A
UTO
RTS (H
ARDWARE
) F
LOW
C
ONTROL
....................................................................................... 13
2.13 A
UTO
RTS H
YSTERESIS
................................................................................................................. 13
2.14 A
UTO
CTS F
LOW
C
ONTROL
........................................................................................................... 13
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
.............................................................................................................. 14
2.15 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................... 14
T
ABLE
6: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
....................................................................................................................... 15
2.16 S
PECIAL
C
HARACTER
D
ETECT
........................................................................................................ 15
2.17 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
........................................................................................... 15
2.18 I
NFRARED
M
ODE
............................................................................................................................. 15
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
................................................................................. 16
2.19 S
LEEP
M
ODE
WITH
A
UTO
W
AKE
-U
P
............................................................................................... 16
2.20 I
NTERNAL
L
OOPBACK
..................................................................................................................... 16
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B........................................................................................................................ 17
3.0 UART INTERNAL REGISTERS ............................................................................................. 18
T
ABLE
7: UART CHANNEL A AND B UART INTERNAL REGISTERS............................................................................................. 18
相關PDF資料
PDF描述
XR16C2850IP40 3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850CJ DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850CM DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850CP DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IJ DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
相關代理商/技術參數(shù)
參數(shù)描述
XR16C2850IM-F 功能描述:UART 接口集成電路 2.97V-5.5V 128B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2850IMTR-F 制造商:Exar Corporation 功能描述:XR16C2850IMTR-F
XR16C2850IP 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IP40 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
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