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參數(shù)資料
| 型號： | XR16C2852IJ-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 29/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 128B 44PLCC |
| 標準包裝： | 27 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 其它名稱： | 1016-1659 XR16C2852IJ-F-ND |
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xr
XR16C2852
REV. 2.1.1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
35
4.15
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x12 for XR16C2852). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.16
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.17
Trigger Level / FIFO Data Count Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.18
FIFO Data Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Register
which is located in the general register set when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
4.19
Feature Control Register (FCTR) - Read/Write
This register controls the XR16C2852 new functions.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See Table 13 on page 34 for more details.
FCTR[2]: IrDa RX Inversion
Logic 0 = Select RX input as encoded IrDa data.
Logic 1 = Select RX input as active high encoded IrDa data.
FCTR[3]: Auto RS-485 Direction Control
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from low to high one bit time after the last stop bit of the last character is shifted out. Also,
the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS#
output pin will automatically return to a logic low when a data byte is loaded into the TX FIFO.
FCTR[5:4]: Transmit/Receive Trigger Table Select
TABLE 14: TRIGGER TABLE SELECT
FCTR BIT-5
FCTR BIT-4
TABLE
0
Table-A (TX/RX)
0
1
Table-B (TX/RX)
1
0
Table-C (TX/RX)
1
Table-D (TX/RX)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2852IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-16C450CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C450CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C452CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C550CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
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