REV. 2.1.1 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 41 AC ELECTRICAL CHARACTERISTICS TA=0
參數(shù)資料
型號: XR16C2852IJ-F
廠商: Exar Corporation
文件頁數(shù): 36/51頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1659
XR16C2852IJ-F-ND
xr
XR16C2852
REV. 2.1.1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
41
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
CONDITIONS
CLK
Clock Pulse Duration
30
20
ns
OSC
Oscillator Frequency
8
24
MHz
OSC
External Clock Frequency
33
50
MHz
TAS
Address Setup Time
10
5
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "DC YYWW" and older)
10
5
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "F2 YYWW" and newer)
0
ns
TCS
Chip Select Width
66
50
ns
TRD
IOR# Strobe Width
35
25
ns
TDY
Read Cycle Delay
40
30
ns
TRDV
Data Access Time
50
35
ns
TDD
Data Disable Time
0
35
0
25
ns
TWR
IOW# Strobe Width
40
25
ns
TDY
Write Cycle Delay
40
30
ns
TDS
Data Setup Time
10
5
ns
TDH
Data Hold Time
10
5
ns
TWDO
Delay From IOW# To Output
50
40
ns
100 pF load
TMOD
Delay To Set Interrupt From MODEM Input
40
35
ns
100 pF load
TRSI
Delay To Reset Interrupt From IOR#
40
35
ns
100 pF load
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
40
ns
100 pF load
TSI
Delay From Stop To Interrupt
45
40
ns
TINT
Delay From Initial INT Reset To Transmit Start
8
24
8
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
45
40
ns
TSSR
Delay From Stop To Set RXRDY#
1
Bclk
TRR
Delay From IOR# To Reset RXRDY#
45
40
ns
TWT
Delay From IOW# To Set TXRDY#
45
40
ns
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