REV. 2.3.1 12 2.7 Internal Registers The 850 has a set of enhanced registers fo" />
參數(shù)資料
型號： XR16C850IM-F
廠商： Exar Corporation
文件頁數(shù)： 4/56頁
文件大小： 0K
描述： IC UART FIFO 128B 48TQFP
標準包裝： 250
特點： *
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1656
XR16C850IM-F-ND
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
12
2.7
Internal Registers
The 850 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad register
(SPR).
Beyond the general 16C550 features and capabilities, the 850 offers enhanced feature registers (EMSR, TRG,
FC, FCTR, EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, Xon/Xoff
software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level control,
and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0, UART
2.8
DMA Mode
The DMA Mode (a legacy term) in this document does not mean “Direct Memory Access” but refers to data
block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins.
The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation.
The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data.
The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the
transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 850 activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1),
the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence
determined by the programmed trigger level. In this mode, the 850 sets the TXRDY# pin when the transmit
FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table
shows their behavior.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
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