REV. 2.3.1 54 NOTICE EXAR Corporation reserves the right to make changes to the produc" />
參數(shù)資料
型號： XR16C850IM-F
廠商： Exar Corporation
文件頁數(shù)： 50/56頁
文件大?。?/td> 0K
描述： IC UART FIFO 128B 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點： *
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1656
XR16C850IM-F-ND
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
54
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet August 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
DATE
REVISION
DESCRIPTION
February 2000
Rev 1.0.0
Initial datasheet.
April 2002
Rev 2.0.0
Changed to standard style format. Internal Registers are described in the order they
are listed in the Internal Register Table. Clarified timing diagrams. Corrected Auto
RTS Hysteresis table. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and tim-
ing symbols. Added TAH, TCS and OSC.
January 2003
Rev 2.1.0
Changed to single column format. Added Factory Test Mode description and work-
around.
May 2003
Rev 2.1.1
Corrected patent number on first page.
June 2003
Rev 2.2.0
Added and Updated Device Status in Ordering Information: 40-pin PDIP and 52-pin
QFP are discontinued.
March 2004
Rev 2.3.0
Devices with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1) and have 0 ns address hold time (TAH). Factory test mode entry
(SEE”FACTORY TEST MODE” ON PAGE 7. ) was improved and DREV register was
updated to 0x06. In addition, the packages are now in Green Molding Compound.
August 2005
Rev 2.3.1
Removed discontinued packages (40-pin PDIP and 52-pin QFP) from Ordering Infor-
mation.
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