參數(shù)資料
型號(hào): XR16C854CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
中文描述: 4 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù): 27/51頁
文件大?。?/td> 476K
代理商: XR16C854CQ
XR16C854
27
Rev. 1.00P
FCR BIT-3:
Logic 0 = Set DMA mode 0. (normal default condi-
tion)
Logic 1 = Set DMA mode 1.
Transmit operation in mode 0:
When the 854 is in the ST16C450 mode (FIFOs
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Receive operation in mode 0:
When the 854 is in mode 0 (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode 1:
When the 854 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Receive operation in mode 1:
When the 854 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = none)
The XR16C854 provide 4 user selectable trigger
levels, The FCTR Bits 4-5 selects one of the following
table. These bits are used to set the trigger level for the
transmit FIFO interrupt. The XR16C854 will issue a
transmit empty interrupt when number of characters in
FIFO drops below the selected trigger level.
TRIGGER TABLE-A (Transmit)
Default setting after reset ST16C550 mode
BIT-5
BIT-4
FIFO trigger level
X
X
None
TRIGGER TABLE-B (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
16
8
24
30
TRIGGER TABLE-C (Transmit)
BIT-5
BIT-4
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
32
56
TRIGGER TABLE-D (Transmit)
BIT-5
BIT-4
FIFO trigger level
X
X
User programmable
Trigger levels
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