參數(shù)資料
型號: XR16L2552
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述: 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁數(shù): 46/47頁
文件大?。?/td> 748K
代理商: XR16L2552
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.1.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
EATURES
.....................................................................................................................................................1
F
IGURE
1. XR16L2552 B
LOCK
D
IAGRAM
......................................................................................................................................... 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENTS
................................................................................................................................................... 2
ORDERING
INFORMATION
.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................7
2.1 CPU INTERFACE .............................................................................................................................................. 7
F
IGURE
3. XR16L2552 D
ATA
B
US
I
NTERCONNECTIONS
.................................................................................................................. 7
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7
2.3 DEVICE RESET ................................................................................................................................................ 7
2.4 DEVICE IDENTIFICATION AND REVISION ..................................................................................................... 7
2.5 CHANNEL A AND B SELECTION .................................................................................................................... 8
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
............................................................................................................................................... 8
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.7 SIMULTANEOUS WRITE TO CHANNEL A AND B ......................................................................................... 8
2.8 DMA MODE ....................................................................................................................................................... 8
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
............................................................................................. 9
2.9 INTA AND INTB OUPUTS ................................................................................................................................ 9
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
........................................................................................................ 9
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
............................................................................................................... 9
2.10 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 9
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
............................................................................................................................... 10
2.11 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 10
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
.......................................................................................... 10
F
IGURE
6. O
PERATING
F
REQUENCY
C
HART
. R
EQUIRES
A
2K
OHMS
PULL
-
UP
RESISTOR
ON
XTAL2
PIN
TO
INCREASE
OPERATING
SPEED
11
T
ABLE
5: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
...................................................................... 11
2.12 TRANSMITTER ............................................................................................................................................. 12
2.12.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 12
2.12.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 12
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
.............................................................................................................. 12
2.12.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 12
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
..................................................................................... 13
2.13 RECEIVER .................................................................................................................................................... 13
2.13.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................... 14
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
....................................................................... 14
2.14 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 15
2.15 AUTO CTS FLOW CONTROL ..................................................................................................................... 15
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
....................................................................................................... 16
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 17
T
ABLE
6: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................................................... 17
2.17 SPECIAL CHARACTER DETECT ............................................................................................................... 17
2.18 INFRARED MODE ........................................................................................................................................ 18
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 18
2.19 SLEEP MODE WITH AUTO WAKE-UP ....................................................................................................... 19
2.20 INTERNAL LOOPBACK .............................................................................................................................. 20
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B ................................................................................................................ 20
3.0 UART INTERNAL REGISTERS ...........................................................................................................21
T
ABLE
7: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 21
T
ABLE
8: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1......................................... 22
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................23
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 23
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 23
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................... 23
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 23
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