參數(shù)資料
型號: XR16L2751
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述: 2.25V至5.5V的杜阿爾特64字節(jié)FIFO和省電
文件頁數(shù): 12/52頁
文件大?。?/td> 618K
代理商: XR16L2751
á
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
12
prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2
16
-1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter
for data bit shifting and
receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL =
0x01 and DLM = 0x00) upon power up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
Table 6
shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
(
DEFAULT
)
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM
P
ROGRAM
V
ALUE
(HEX)
DLL
P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
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XR16L2751CM 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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