參數(shù)資料
型號(hào)： XR16L2751
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述： 2.25V至5.5V的杜阿爾特64字節(jié)FIFO和省電
文件頁(yè)數(shù)： 51/52頁(yè)
文件大?。?/td> 618K
代理商： XR16L2751
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
á
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
.............................................................................................................................................1
F
EATURES
...................................................................................................................................................1
F
IGURE
1. XR16L2751 B
LOCK
D
IAGRAM
................................................................................................................................................. 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
............................................................................................................................................................. 2
ORDERING
INFORMATION
..............................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION ...................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 7
2.1 CPU I
NTERFACE
................................................................................................................................. 7
F
IGURE
3. XR16L2751 T
YPICAL
I
NTEL
/M
OTOROLA
D
ATA
B
US
I
NTERCONNECTIONS
.................................................................................. 8
2.2 5-V
OLT
T
OLERANT
I
NPUTS
................................................................................................................... 9
2.3 D
EVICE
H
ARDWARE
R
ESET
.................................................................................................................. 9
2.4 D
EVICE
I
DENTIFICATION
AND
R
EVISION
................................................................................................. 9
2.5 C
HANNEL
A
AND
B S
ELECTION
............................................................................................................. 9
2.6 C
HANNEL
A
AND
B I
NTERNAL
R
EGISTERS
............................................................................................. 9
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
IN
16 M
ODE
.................................................................................................................................... 9
T
ABLE
2: C
HANNEL
A
AND
B S
ELECT
IN
68 M
ODE
.................................................................................................................................... 9
2.7 DMA M
ODE
...................................................................................................................................... 10
2.8 INTA
AND
INTB O
UTPUTS
................................................................................................................. 10
T
ABLE
3: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
.................................................................................................. 10
T
ABLE
4: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
.............................................................................................................. 10
T
ABLE
5: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
..................................................................................................................... 10
2.9 C
RYSTAL
O
SCILLATOR
OR
E
XTERNAL
C
LOCK
I
NPUT
............................................................................ 11
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
...................................................................................................................................... 11
2.10 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
...................................................................................... 11
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
................................................................................................. 11
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
............................................................................................................................. 12
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
.............................................................................. 12
2.11 T
RANSMITTER
.................................................................................................................................. 13
2.11.1 Transmit Holding Register (THR) - Write Only....................................................................................... 13
2.11.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 13
2.11.3 Transmitter Operation in FIFO Mode...................................................................................................... 13
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
...................................................................................................................... 13
2.12 RECEIVER .................................................................................................................................... 14
2.12.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 14
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
............................................................................................. 14
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
........................................................................................................................... 15
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
............................................................................... 15
2.13 A
UTO
RTS (H
ARDWARE
) F
LOW
C
ONTROL
....................................................................................... 16
2.14 A
UTO
RTS H
YSTERESIS
................................................................................................................. 16
2.15 A
UTO
CTS F
LOW
C
ONTROL
............................................................................................................ 16
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
.............................................................................................................. 17
2.16 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................... 18
2.17 S
PECIAL
C
HARACTER
D
ETECT
........................................................................................................ 18
2.18 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
............................................................................................ 18
T
ABLE
7: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
....................................................................................................................... 18
2.19 I
NFRARED
M
ODE
............................................................................................................................ 19
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
................................................................................. 19
2.20 S
LEEP
M
ODE
WITH
A
UTO
W
AKE
-U
P
AND
P
OWER
S
AVE
F
EATURE
..................................................... 20
2.21 I
NTERNAL
L
OOPBACK
...................................................................................................................... 21
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B........................................................................................................................ 21
3.0 UART INTERNAL REGISTERS ............................................................................................. 22
T
ABLE
8: UART CHANNEL A AND B UART INTERNAL REGISTERS.............................................................................................. 22
T
ABLE
9: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1 ................................................. 23
4.0 INTERNAL Register descriptions ........................................................................................ 24
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