參數(shù)資料
型號: XR16L2751
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述: 2.25V至5.5V的杜阿爾特64字節(jié)FIFO和省電
文件頁數(shù): 41/52頁
文件大?。?/td> 618K
代理商: XR16L2751
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
á
41
asleep. Floating inputs may result in sleep currents in the mA range. For Powersave, the UART internally
isolates all of these inputs therefore not requiring them to remain steady.
AC ELECTRICAL CHARACTERISTICS
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
2.5- 5.0V +/-10%
S
YMBOL
P
ARAMETER
L
IMITS
2.5
M
IN
M
AX
L
IMITS
3.3
M
IN
M
AX
L
IMITS
5.0
M
IN
M
AX
U
NIT
C
ONDITIONS
CLK
Clock Pulse Duration
50
50
17
ns
OSC
Oscillator Frequency
16
20
24
MHz
OSC
External Clock Frequency
24
33
50
MHz
T
AS
Address Setup Time (16 Mode)
15
10
5
ns
T
AH
Address Hold Time (16 Mode)
15
10
5
ns
T
CS
Chip Select Width (16 Mode)
66
66
50
ns
T
RD
IOR# Strobe Width (16 Mode)
50
35
25
ns
T
DY
Read Cycle Delay (16 Mode)
50
40
30
ns
T
RDV
Data Access Time (16 Mode)
50
50
35
ns
T
DD
Data Disable Time (16 Mode)
0
35
0
35
0
25
ns
T
WR
IOW# Strobe Width (16 Mode)
40
40
25
ns
T
DY
Write Cycle Delay (16 Mode)
50
40
30
ns
T
DS
Data Setup Time (16 Mode)
15
10
5
ns
T
DH
Data Hold Time (16 Mode)
15
10
5
ns
T
ADS
Address Setup (68 Mode)
15
10
5
ns
T
ADH
Address Hold (68 Mode)
15
10
5
ns
T
RWS
R/W# Setup to CS# (68 Mode)
15
10
5
ns
T
RDA
Read Data Access (68 mode)
50
45
35
ns
T
RDH
Read Data Hold (68 mode)
35
30
25
ns
T
WDS
Write Data Setup (68 mode)
15
10
5
ns
T
WDH
Write Data Hold (68 Mode)
15
10
5
ns
T
RWH
CS# De-asserted to R/W# De-
asserted (68 Mode)
15
10
5
ns
T
CSL
CS# Width (68 Mode)
50
40
30
ns
T
CSD
CS# Cycle Delay (68 Mode)
50
40
30
ns
T
WDO
Delay From IOW# To Output
50
50
40
ns
100 pF load
T
MOD
Delay To Set Interrupt From
MODEM Input
50
40
35
ns
100 pF load
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XR16L2751CM 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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