REV. 1.2.3 34 MSR[7]: CD Input Status Normally this bit is the complement of the " />
參數資料
型號: XR16L2751CMTR-F
廠商: Exar Corporation
文件頁數: 28/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標準包裝: 1,500
特點: *
通道數: 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.2.3
34
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10
Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11
Enhanced Mode Select Register (EMSR)
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 13: SCRATCHPAD SWAP SELECTION
FCTR[6]
EMSR[1] EMSR[0] Scratchpad is
0
X
Scratchpad
1
0
RX FIFO Counter Mode
1
0
1
TX FIFO Counter Mode
1
0
RX FIFO Counter Mode
1
Alternate RX/TX FIFO
Counter Mode
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[2]: Reserved
EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion
Logic 0 = RTS# output is LOW during TX and HIGH during RX (default, compatible with 16C2850).
Logic 1 = RTS# output is HIGH during TX and LOW during RX.
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