REV. 1.2.3 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 21 2.21 Internal Loopback The 2751 UART provides an inte" />
參數(shù)資料
型號(hào): XR16L2751IM-F
廠商: Exar Corporation
文件頁數(shù): 14/50頁
文件大小: 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1452
XR16L2751IM-F-ND
XR16L2751
REV. 1.2.3
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
21
2.21
Internal Loopback
The 2751 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held HIGH or mark condition while the CTS#, DSR# CD# and
RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during loopback test else upon
exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/CTS hardware
flow control is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/
G
en
eral
Purpos
e
Cont
rol
Logic
Inte
rn
a
lD
a
ta
Bus
L
ines
and
Co
ntrol
Signa
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
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