REV. 1.2.3 4 INTB 29 O When 16/68# pin is HIGH for Intel bus interface, this outp" />
參數(shù)資料
型號: XR16L2751IM-F
廠商: Exar Corporation
文件頁數(shù): 34/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 64B DUAL 48TQFP
標準包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1452
XR16L2751IM-F-ND
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.2.3
4
INTB
29
O
When 16/68# pin is HIGH for Intel bus interface, this output becomes channel B inter-
rupt output. The output state is defined by the user and through the software setting
of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when
MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output is not used and will
stay at logic zero level. Leave this output unconnected.
TXRDYA#
43
O
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel A.
RXRDYA#
31
O
UART channel A Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel A.
TXRDYB#
6
O
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B.
RXRDYB#
18
O
UART channel B Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel B.
MODEM OR SERIAL I/O INTERFACE
TXA
7
O
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
RXA
5
I
UART channel A Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles at logic 0 but can be
inverted by software control prior going to the decoder, see MCR[6] and FCTR[2].
RTSA#
33
O
UART channel A Request-to-Send (active low) or general purpose output. This out-
put must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
CTSA#
38
I
UART channel A Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be con-
nected to VCC when not used.
DTRA#
34
O
UART channel A Data-Terminal-Ready (active low) or general purpose output.
DSRA#
39
I
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
CDA#
40
I
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
RIA#
41
I
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
OP2A#
32
O
Output Port 2 Channel A - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTA is set to the level
mode and OP2A# output LOW. When MCR[3] is set to a logic 0, INTA is set to the
three state mode and OP2A# is HIGH. See MCR[3]. This output must not be used as
a general output when the interrupt output is used else it will disturb the INTA output
functionality.
Pin Description
NAME
48-TQFP
PIN #
TYPE
DESCRIPTION
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