參數(shù)資料
型號(hào)： XR16L2751IM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 618K
代理商： XR16L2751IM
á
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
26
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 10
, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
4.5.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff or Special character interrupt is cleared by a read to ISR.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
相關(guān)PDF資料
PDF描述
XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L2751IM-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2751IMTR-F 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L2751IMTR-F
XR16L2752 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO
XR16L2752CJ 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO
XR16L2752CJ-0A-EB 功能描述:UART 接口集成電路 Supports L2750 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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