參數(shù)資料
型號(hào)： XR16L2751IM
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 52/52頁(yè)
文件大小： 618K
代理商： XR16L2751IM
á
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
II
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
- O
NLY
........................................................................... 24
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-O
NLY
......................................................................... 24
4.3 B
AUD
R
ATE
G
ENERATOR
D
IVISORS
(DLL
AND
DLM) - R
EAD
/W
RITE
................................................... 24
4.4 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.......................................................................... 25
4.4.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 25
4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 25
4.5 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 26
4.5.1 Interrupt Generation:................................................................................................................................ 26
4.5.2 Interrupt Clearing: .................................................................................................................................... 26
4.6 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 27
T
ABLE
10: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................. 27
4.7 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................ 29
T
ABLE
11: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
................................................................................................... 29
T
ABLE
12: P
ARITY
SELECTION
................................................................................................................................................................ 30
4.8 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
....... 31
4.9 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
..................................................................................... 32
4.10 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................. 33
4.11 S
CRATCHPAD
R
EGISTER
(SPR) - R
EAD
/W
RITE
................................................................................ 34
4.12 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR) ................................................................................. 34
T
ABLE
13: S
CRATCHPAD
S
WAP
S
ELECTION
............................................................................................................................................ 34
4.13 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
.................................................................................. 35
4.14 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
.............................................. 35
4.15 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
................................................................. 35
T
ABLE
14: A
UTO
RTS H
YSTERESIS
....................................................................................................................................................... 35
4.16 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 36
4.17 T
RIGGER
L
EVEL
(TRG) - W
RITE
-O
NLY
............................................................................................ 36
4.18 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
........................................................................... 36
4.19 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/W
RITE
.................................................................... 36
T
ABLE
15: T
RIGGER
T
ABLE
S
ELECT
....................................................................................................................................................... 36
4.20 E
NHANCED
F
EATURE
R
EGISTER
(EFR) ........................................................................................... 37
T
ABLE
16: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 37
4.21 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 39
T
ABLE
17: UART RESET CONDITIONS FOR CHANNEL A AND B................................................................................................... 39
ABSOLUTE MAXIMUM RATINGS ..................................................................................40
ELECTRICAL CHARACTERISTICS................................................................................40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)40
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................40
AC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................41
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
2.5- 5.0V +/-10%...............41
F
IGURE
14. C
LOCK
T
IMING
.................................................................................................................................................................... 42
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A & B......................................................................................................... 43
F
IGURE
16. 16 M
ODE
(I
NTEL
) D
ATA
B
US
R
EAD
T
IMING
.......................................................................................................................... 44
F
IGURE
17. 16 M
ODE
(I
NTEL
) D
ATA
B
US
W
RITE
T
IMING
......................................................................................................................... 44
F
IGURE
18. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
R
EAD
T
IMING
.................................................................................................................. 45
F
IGURE
19. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
W
RITE
T
IMING
................................................................................................................ 45
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B................................................................. 46
F
IGURE
21. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B............................................................... 46
F
IGURE
22. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A & B............................................... 47
F
IGURE
23. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A & B................................................ 47
F
IGURE
24. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B................................... 48
F
IGURE
25. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B.................................... 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)..............................................49
R
EVISION
H
ISTORY
....................................................................................................................................50
TABLE OF CONTENTS ................................................................................................................................. I
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