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參數(shù)資料
| 型號： | XR16M2752IJ-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 7/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR M2752-B 44PLCC |
| 標準包裝： | 1 |
| 系列： | * |
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XR16M2752
15
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.12
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.13
Auto RTS Hysteresis
The M2752 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return
LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described
conditions, the M2752 will continue to accept data until the receive FIFO gets full. The Auto RTS function is
initiated when the RTS# output pin is asserted LOW (RTS On). Table 13 shows the complete details for the
Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The
hysteresis values for Tables A-C are the next higher and next lower trigger levels in the corresponding table.
2.14
Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-3. By default, it de-asserts RTS# (HIGH) output following the last stop bit of the last character that has been
transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the
host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The
transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex
direction control output can be inverted by enabling EMSR bit-3.
2.15
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 10):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16M2752IJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16M2752IJ44-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16M2752IL-0A-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16M2752IL-0A RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR16M2752IL-0B-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16M2752IL Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR16M2752IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
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