XR16M670
24
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
REV. 1.0.1
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER
RD/WR
0/
Modem
Stat. Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
CTS#
Int.
Enable
RTS#
Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
LCR[7] = 0
if EFR[4]=1
or
LCR
≠0xBF
if EFR[4]=0
RTS
CTS
Interrupt
Xoff
Interrupt
0 1 0
FCR
WR
RXFIFO
Trigger
RXFIFO
Trigger
TXFIFO
Trigger
TXFIFO
Trigger
Wake up
Int Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
0 1 1
LCR
RD/WR Divisor
Enable
Set TX
Break
Set
Parity
Even
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR
RD/WR
0/
Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
OP1#
RTS#
Output
Control
DTR#
Output
Control
LCR
≠0xBF
BRG
Pres-
caler
IR Mode
ENable
XonAny
1 0 1
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX Break RX Fram-
ing Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
WR
Fast IR
Enable
9-bit
mode
Disable
RX
Disable
TX
0
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR
≠0xBF
FCTR[6]=0
1 1 1
EMSR
WR
Xoff
interrupt
mode
select
LSR
interrupt
mode
select
0
Invert
RTS in
RS485
mode
Send
TX
imme-
diate
FIFO
count
control
bit-1
FIFO
count
control
bit-0
LCR
≠0xBF
FCTR[6]=1
1 1 1
FC
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0