REV. 1.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CP" />
參數(shù)資料
型號(hào): XR16M670IL32-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 47/50頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16M670-B 32QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16M670
6
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M670 data interface supports the Intel compatible types of CPUs. No clock (oscillator
nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR#
and IOW# inputs. A typical data bus interconnection for Intel mode is shown in Figure 3.
FIGURE 3. XR16M670 TYPICAL INTEL DATA BUS INTERCONNECTIONS
VCC
A0
A1
A2
UART_CS#
IOR#
IOW#
CS#
IOR#
IOW#
UART_INT
INT
Intel Data Bus Interconnections
GND
UART_RESET
RESET
RI#
CD#
DSR#
CTS#
RTS#
DTR#
RX
TX
PwrSave
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
Serial Transceivers of
RS-232
RS-485
RS-422
Or Infrared
POWERSAVE
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