TABLE 9: TRANSMIT AND R
參數(shù)資料
型號: XR16M670IL32-0B-EB
廠商: Exar Corporation
文件頁數(shù): 24/50頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16M670-B 32QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCR BIT-7
FCR BIT-6
FCR BIT-5
FCR BIT-4
RECEIVE TRIGGER
LEVEL
TRANSMIT
TRIGGER LEVEL
COMPATIBILITY
0
1
0
1
0
1
0
1
0
1
0
1
8
16
24
28
16
8
24
30
16C650A, 16V2650 and
16M2650
XR16M670
30
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
REV. 1.0.1
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
BIT-1
BIT-0
BIT-2
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