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參數(shù)資料
| 型號： | XR16V2752IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 49/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR V2752 32QFN |
| 標準包裝： | 1 |
| 系列： | * |
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XR16V2752
7
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The V2752 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in Figure 3
2.2
5-Volt Tolerant Inputs
The V2752 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the V2752 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4
Device Identification and Revision
The XR16V2752 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide
0x0A for the XR16V2752 and reading the content of DLL will provide the revision of the part; for example, a
reading of 0x01 means revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS
VC C
(O P 2 A # )
DS RA #
CT S A #
RT S A #
DT RA #
RX A
TX A
RIA #
CDA #
(O P2 B# )
DS RB #
CT S B #
RT S B #
DT RB #
RX B
TX B
RIB #
CD B #
GN D
A0
A1
A2
UA RT _ C S #
UA RT _ CHS E L
IO R #
IO W #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS #
CHS E L
D0
D1
D2
D3
D4
D5
D6
D7
IO R #
IO W #
UA RT
C h an ne l A
UA RT
C h an ne l B
UA RT _ INT B
UA RT _ INT A
IN T B
IN T A
(R XR D YA# )
TXR D YA#
(R XR D YA# )
T X R D YA#
(R XR D YB# )
TXR D YB#
(R XR D YB# )
T X R D YB#
UA RT _ R E S E T
RE S E T
S e ria l In te rfa c e o f
RS -2 3 2 , RS -4 8 5
S e ria l In te rfa c e o f
RS -2 3 2 , RS -4 8 5
27 50 in t
(B A UDO UT B # )
(B A UDO UT A # )
P ins in p a re nthe s e s be c o m e availa b le th ro u g h th e M F # p in . M F # A /B b e com e s R X R D Y # A /B w h en A F R [2:1] = '1 0 '. M F # A /B be c o m e s O P 2 # A /B
w h en A F R [2:1] = '0 0 '. M F # A /B be c o m e s B A U D O U T # A /B w h en A F R [1:0] = '0 1 '.
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