REV. 1.0.3 2.11 Internal Loopback The V554 UART provides an internal l" />
參數資料
型號: XR16V554IJ-0A-EVB
廠商: Exar Corporation
文件頁數: 10/43頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16V554 68PLCC
標準包裝: 1
系列: *
XR16V554/554D
18
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.3
2.11
Internal Loopback
The V554 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOPBACK
TX A-D
RX A-D
M
ode
m
/
G
e
neral
Purp
ose
Co
ntro
lLogic
In
te
rn
al
Dat
aBu
sLi
nes
an
d
Co
ntro
lSi
gn
als
RTS# A-D
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS# A-D
DTR# A-D
DSR# A-D
RI# A-D
CD# A-D
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
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