REV. 1.0.3 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 s" />
參數(shù)資料
型號(hào)： XR16V554IJ-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 18/43頁
文件大小： 0K
描述： EVAL BOARD FOR XR16V554 68PLCC
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V554/554D
25
REV. 1.0.3
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to LOW for the transmit and receive data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark, HIGH
1
Forced parity to space, LOW
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the V554. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
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XR16V554IJTR-F 功能描述:UART 接口集成電路 XR16V554IJTR-F RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16V554IL 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
XR16V554IL-0A-EVB 功能描述:UART 接口集成電路 Supports V554 48 pin QFN,ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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