FIGURE
參數(shù)資料
型號(hào): XR16V598IQ-0A-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 50/58頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR16V598-A 100QFP
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16V598
54
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.3
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]
TX
IO W #
IN T # *
D0 :D 7
Sta rt
Bit
D0 :D 7
Sto p
Bit
D0 :D 7
T
WR I
T
WR I
T
WR I
* T X in te rrupt is c leared w h en the IS R is read or w hen data is loade d in to the TH R .
IS R is re a d
(Loa ding d a ta
in to T H R )
(U nloa ding)
IE R [1 ]
enab le d
RX
IO R#
INT#
D0:D7
S
RX FIFO fills up to RX
Trigger Level or RX Data
Tim eout
RX FIFO drops
below RX
Trigger Level
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
T
RR
T
RR I
T
SSI
(Reading data out
of RX FIFO )
TX
IO W #
IN T#*
D0:D 7
S
D0:D 7
T
D0:D 7
S
D0:D 7
S
T
D0:D 7
S
T
D0:D 7
S
T
Start
Bit
Stop
Bit
(U nloading)
(Loading data
into FIFO )
Last D ata B yte
Transm itted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TX FIFO
Em pty
T
S
T
SI
IS R is read
IE R [1]
enabled
IS R is read
*TX interrupt is cleared when the IS R is read or when TX FIFO fills up to the trigger level.
T
WR I
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