TABLE
參數(shù)資料
型號(hào): XR16V598IQ-0B-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 25/58頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16V598-A 100QFP
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16V598
31
REV. 1.0.3
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
0 0 0 0
RHR
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
THR
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
DLL
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
DLM
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 1 0
DLD
R/W
0
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
IER
R/W
0/
0
Modem
Status Int.
Enable
RX Line
Status Int.
Enable
TX Ready
Int.
Enable
RX Data
Int.
Enable
LCR[7]=0
CTS/
DSR# Int.
Enable
RTS/
DTR# Int.
Enable
Xon/Xoff/
Sp. Char.
Int.
Enable
0 0 1 0
ISR
R
FIFOs
Enable
FIFOs
Enable
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
LCR[7]=0
Delta-
Flow Cntl
Xoff/special
char
0 0 1 0
FCR
W
RX FIFO
Trigger
RX FIFO
Trigger
0/
DMA
Mode
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
LCR[7]=0
TX FIFO
Trigger
TX FIFO
Trigger
0 0 1 1
LCR
R/W
Divisor
Enable
Set TX
Break
Set Parity Even Par-
ity
Parity
Enable
Stop Bits
Word
Length
Bit-1
Word
Length
Bit-0
0 1 0 0
MCR
R/W
0/
Internal
Loopback
Enable
(OP2)1
(OP1)1
RTS# Pin
Control
DTR# Pin
Control
BRG
Prescaler
IR
Enable
XonAny
TX char
Immedi-
ate
RTS/DTR
Flow Sel
0 1 0 1
LSR
R
RX FIFO
ERROR
Transmit-
ter Empty
TX FIFO
Empty
RX Break
RX Fram-
ing Error
RX Parity
Error
RX Over-
run
RX Data
Ready
0 1 1 0
MSR
R
CD
RI
DSR
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
MSR
W
RS485
DLY-3
RS485
DLY-2
RS485
DLY-1
RS485
DLY-0
Disable
TX
Disable
RX
0
9-bit
Mode
0 1 1 1
SPR
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
User Data
1 0 0 0
FCTR
R/W
0
Auto
RS485
Enable
Invert IR
RX Input
0
1 0 0 1
EFR
R/W
Auto
CTS/DSR
Enable
Auto
RTS/DTR
Enable
Special
Char
Select
Enable
IER [7:5],
ISR [5:4],
FCR[5:4],
MCR[7:5,
3:2]
MSR[7:0]
Software
Flow Cntl
Bit-3
Software
Flow Cntl
Bit-2
Software
Flow Cntl
Bit-1
Software
Flow Cntl
Bit-0
1 0 1 0
Rsvd
R
0
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