參數(shù)資料
型號: XR17C152CM-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 38/62頁
文件大小: 0K
描述: EVAL BOARD FOR XR17C152 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
á
XR17C152
REV. 1.2.0
5V PCI BUS DUAL UART
43
MSR[5]: DSR Input Status
This input may be used for auto DTR/DSR flow control function, see “Section 4.4, Automatic Hardware (RTS/
CTS or DTR/DSR) Flow Control Operation” on page 28 for complete details. If automatic hardware flow control
is not used, this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the
DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem
interface is not used.
MSR[6]: RI Input Status
This bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR
register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
This bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR
register. The CD# input may be used as a general purpose input
4.8.11
Modem Status Register (MSR) - Write-Only
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around
from transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks. Table 16 shows the selection. The bits are enabled by EFR bit-4.
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
DELAY IN DATA BIT(S) TIME
0000
0
0001
1
0010
2
0011
3
0100
4
9101
5
0110
6
0111
7
1000
8
1001
9
1010
10
1011
11
1100
12
1101
13
1110
14
1111
15
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