參數(shù)資料
型號： XR17C152CM-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 4/62頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17C152 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR17C152
á
5V PCI BUS DUAL UART
REV. 1.2.0
12
1.2.1
The Interrupt Status Register
The XR17C152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme uses bits 0 to 1 of an 8-bit indicator (INT0) representing
channels 0 to 1 of the XR17C152, respectively. This permits the interrupt routine to quickly vector and serve
that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt
status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service.
INT0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the
interrupts are encoded into a 3-bit code per channel. This 3-bit code represents 7 interrupts corresponding to
individual UART’s transmitter, receiver, line status, modem port status. INT1 register provides the 6-bit interrupt
status for both channels. Bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1.
Bits 14 to 31 are reserved and remain at logic zero. Both channels interrupt status are available with a single
DWORD read operation. This feature allows the host to quickly vector and serve the interrupts, reducing
service interval, hence, reducing host bandwidth requirements. Figure 4 shows the 4-byte interrupt register
and its make up.
A special interrupt condition is generated by the 152 when it wakes up from sleep mode. This special interrupt
is cleared by reading the INT0 register. If there are not any other interrupts pending, the value read from INT0
would be 0x00.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-1
indicates channel 1. Logic 1 indicates that a channel has requested for service. Bits 2 to 7 are reserved and
remain at logic 0 The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
Registers INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and channel 1 with bits [13:11]. The 3 bit encoding and their priority
order are shown below in Table 5 on page 13. The Timer and MPIO interrupts are for the device and therefore
they exist within channel 0 (bits [10:8]) only.
GLOBAL INTERRUPT REGISTER (DWORD)
[default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
The INT0 register provides status for each channel
IN T0 R eg iste r
Ind ividua l U A R T C han nel Interru pt S tatu s
Rs vd
Rs vd Rs vd Ch-1 Ch-0
B it-7
B it-6
B it-5 B it-4
B it-3
B it-2
B it-1
B it-0
Rs vd Rs vd Rs vd
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