REV. 1.3.2 5V PCI BUS QUAD UART 13 1.2.1 The Interrupt Status Register The XR17C154 has a 32-bit wide register [INT0, INT1, INT2 an" />
參數(shù)資料
型號(hào)： XR17C154CV-0A-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 5/62頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17C154-A 144TQF
標(biāo)準(zhǔn)包裝： 1
系列： *
xr
XR17C154
REV. 1.3.2
5V PCI BUS QUAD UART
13
1.2.1
The Interrupt Status Register
The XR17C154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme uses bits 0 to 3 of an 8-bit indicator (INT0) representing
channels 0 to 3 of the XR17C154, respectively. This permits the interrupt routine to quickly vector and serve
that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt
status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service.
Other bits in the INT0 register provide indication for the other channels with bit-3 representing UART channel 3
respectively. Bits 4 through 7 are reserved and remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 12-bit interrupt status
for all 4 channels. Bits 8, 9 and 10 representing channel 0 and bits 17, 18 and 19 representing channel 3
respectively. Bits 20 to 31 are reserved and remain at a logic 0. All 4 channel interrupts status are available
with a single DWORD read operation. This feature allows the host quickly vectors and serves the interrupts,
reducing service interval, hence, reduce host bandwidth requirement. Figure 4 shows the 4-byte interrupt
register and its make up.
A special interrupt condition is generated by the 154 when it wakes up from sleep mode. This special interrupt
is cleared by reading the INT0 register. If there are not any other interrupts pending, the value read from INT0
would be 0x00.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-3
indicates channel 3. Logic 1 indicates that a channel has called for service. Bits 4 to 7 are reserved and remain
at a logic 0. The interrupt bit clears after reading the appropriate register of the interrupting channel register,
see Interrupt Clearing section.
INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3 bit encoding and their
priority order are shown below in Table 5. The Timer and MPIO interrupts are for the device and therefore they
exist within channel 0 space (bits [10:8]) and not in other channel.
GLOBAL INTERRUPT REGISTER (DWORD)
[default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
The INT0 register provides individual status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Rsvd
Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd Rsvd Rsvd
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