參數(shù)資料
型號: XR17C154IV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: Tools, Heatgun; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述: 4 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁數(shù): 22/62頁
文件大?。?/td> 721K
代理商: XR17C154IV
XR17C154
5V PCI BUS QUAD UART
á
REV. 1.3.0
22
3.1.2
The XR17C154 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), and 0x780 (channel 3). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
Special Rx FIFO
Data Unloading at locations 0x180, 0x380, 0x580, and 0x780
3.1.3
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
and 0x700 (channel 3).
Tx FIFO
Data Loading at locations 0x100, 0x300, 0x500, 0x700
R
EAD
RX FIFO,
WITH N
O
E
RRORS
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
R
EAD
RX FIFO,
WITH
LSR
E
RRORS
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 3 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500 and 0x0700
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
the Configuration Register Address 0x0180 and 0x0380
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