參數(shù)資料
型號: XR17C154IV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: Tools, Heatgun; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述: 4 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁數(shù): 27/62頁
文件大?。?/td> 721K
代理商: XR17C154IV
á
REV. 1.3.0
XR17C154
5V PCI BUS QUAD UART
27
4.3
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 1-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out function
when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths as
defined by LCR[1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit-0.
4.3.1
Receive Holding Register (RHR) - Read-Only
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 3 extra bits are for the error flags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error flags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
4.3.2
Receiver Operation in non-FIFO Mode
Receiver
F
IGURE
12. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X Clock
(8XMODE Register)
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
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