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參數(shù)資料
| 型號(hào)： | XR17C154IV |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Tools, Heatgun; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| 中文描述： | 4 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 34/62頁 |
| 文件大小： | 721K |
| 代理商： | XR17C154IV |
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XR17C154
5V PCI BUS QUAD UART
á
REV. 1.3.0
34
N
OTE
:
MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17C154. They are present for 16C550
compatibility during Internal loopback, see
Figure 16
.
4.8
4.8.1
See
“Section 4.3, Receiver” on page 27
for complete details.
4.8.2
Transmit Holding Register (THR) - Write-Only
See
“Section 4.2, Transmitter” on page 25
for complete details.
4.8.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The baud rate is programmed through registers DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See
“Section 4.1, Programmable Baud Rate Generator” on page 24
for more detail.
4.8.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and
also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
IER
VERSUS
R
ECEIVE
FIFO I
NTERRUPT
M
ODE
O
PERATION
When the receive FIFO (FCR bit-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A.
The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
IER
VERSUS
R
ECEIVE
/T
RANSMIT
FIFO P
OLLED
M
ODE
O
PERATION
When FCR BIT-0 equals a logic 1 for FIFO enable, resetting IER bits 0-3 enables the 158 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR or RX FIFO.
B.
LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C.
LSR BITS 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR is empty.
E.
LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F.
LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
Registers
Receive Holding Register (RHR) - Read-Only
1 1 0 0
XCHAR
R
0
0
0
0
0
0
Xon Det.
Indicator
Xoff Det.
Indicator
Self-clear
after read
1 1 0 0
XOFF1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 1
XOFF2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 0
XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 1
XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
T
ABLE
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4.
A
DDRESS
A3-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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相關(guān)代理商/技術(shù)參數(shù) |
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| XR17C154IV-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17C154IVTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C154IVTR-F |
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| XR17C158CV | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17C158CV-0A-EVB | 功能描述:UART 接口集成電路 Supports C158 144 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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