參數(shù)資料
型號: XR17D152
廠商: Exar Corporation
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
中文描述: 通用(3.3V和5V)PCI總線的雙UART
文件頁數(shù): 15/68頁
文件大?。?/td> 772K
代理商: XR17D152
á
REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
15
.
F
IGURE
6. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3
T
ABLE
5: UART C
HANNEL
[1:0] I
NTERRUPT
S
OURCE
E
NCODING
P
RIORITY
B
IT
[
N
+2]
B
IT
[
N
+1]
B
IT
[
N
]
I
NTERRUPT
S
OURCE
(
S
)
x
0
0
0
None
1
0
0
1
RXRDY and RX Line Status (logic OR of LSR[4:1])
2
0
1
0
RXRDY Time-out
3
0
1
1
TXRDY, THR or TSR (auto RS485 mode) empty
4
1
0
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5
1
0
1
Reserved.
6
1
1
0
MPIO pin(s). Available only in channel 0, reserved in channel 1.
7
1
1
1
TIMER Time-out. Available only in channel 0, reserved channel 1.
T
ABLE
6: UART C
HANNEL
[1:0] I
NTERRUPT
C
LEARING
:
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
Rsvd
Rsvd
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Rsvd
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Rsvd
Rsvd Ch-1 Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
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